产品介绍

74LVX373 Low Voltage Octal D-Type Latch 3-State non inverting

The 74LVX373 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power, battery operated and low noise 3.3V applications.

This 8 bit D-Type latch is controlled by a latch enable input (LE) and an output enable input (OE). While the LE input is held at a high level, the Q outputs will follow the data input precisely.

When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data.

While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.

Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage.

This device can be used to interface 5V to 3V. It combines high speed performance with the true CMOS low power consumption.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage

技术特性

• HIGH SPEED:
  • tPD=5.8ns (TYP.) at VCC = 3.3V
• 5V TOLERANT INPUTS
• POWER-DOWN PROTECTION ON INPUTS
• INPUT VOLTAGE LEVEL:
  • VIL= 0.8V, VIH= 2V at VCC =3V
• LOW POWER DISSIPATION:
  • ICC = 4 μA (MAX.) at TA=25˚C
• LOW NOISE:
  • VOLP= 0.3V (TYP.) at VCC =3.3V
• SYMMETRICAL OUTPUT IMPEDANCE:
  • |IOH| = IOL= 4 mA (MIN) at VCC =3V
• BALANCED PROPAGATION DELAYS:
  • tPLH tPHL
• OPERATING VOLTAGE RANGE:
  • VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
• PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373
• IMPROVED LATCH-UP IMMUNITY

74LVX373 订购信息

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