产品介绍

74LVC573A Low Voltage CMOS Octal D-Type Latch Advenced Performance

The 74LVC573A is a low voltage CMOS OCTAL D-TYPE LATCH fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications.

These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.

This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components. It has more speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption.

All inputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

技术特性

• 5V TOLERANT INPUTS
• HIGH SPEED: tPD = 6.8ns (MAX.) at VCC = 3V
• POWER DOWN PROTECTION ON INPUTS AND OUTPUTS
• SYMMETRICAL OUTPUT IMPEDANCE:
  • |IOH| = IOL= 24mA (MIN) at VCC = 3V
• PCI BUS LEVELS GUARANTEED AT 24 mA
• BALANCED PROPAGATION DELAYS:
  • tPLH tPHL
• OPERATING VOLTAGE RANGE:
  • VCC(OPR) = 1.65V to 3.6V (1.2V Data Retention)
• PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 573
• LATCH-UP PERFORMANCE EXCEEDS
  • 500mA (JESD 17)
• ESD PERFORMANCE:
  • HBM > 2000V (MIL STD 883 method 3015);
  • MM > 200V

74LVC573A 订购信息

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