产品介绍

74LCX573 Octal D-Type Latch Non-Inverting (3-State) with 5V Tolerant Input & Output

The 74LCX573 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON-INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs.

These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input. When the LE is taken low, the Q outputs will be latched at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while (OE) is in high level, the outputs will be in a high impedance state.

It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption.

All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

技术特性

• 5V tolerant inputs and outputs
• High speed:
  • tPD = 8.0ns (Max) at VCC = 3V
• Power down protection on inputs and outputs
• Symmetrical output impedance:
  • |IOH| = IOL = 24mA (Min) at VCC= 3V
• PCI bus levels guaranteed at 24mA
• Balanced propagation delays:
  • tPLH tPHL
• Operating voltage range:
  • VCC(Opr) = 2.0V to 3.6V (1.5V Data Retention)
• Pin and function compatible with 74 series 573
• Latch-up performance exceeds 500mA (JESD 17)
• ESD performance:
  • HBM > 2000V (MIL STD 883 method 3015);
  • MM > 200V

74LCX573 订购信息

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