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SN74ABT8543 具有八路寄存总线收发器的扫描测试设备

当前价格: ¥ 0.00/PCS
最小起订:2500PCS
供货总量:100000PCS
发 货 期:1天内发货
所 在 地: 中国 
发布时间:2012-07-31

BDTIC 代理商

商家等级:普通供应商

联系人:吴奇禄

电话:0755-83574989

地址:中国广东省深圳福田区华强北福虹路8号世贸广场B座12F

产品介绍

SN74ABT8543 具有八路寄存总线收发器的扫描测试设备

The 'ABT8543 scan test devices with octal registered bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are functionally equivalent to the 'F543 and 'ABT543 octal registered bus transceivers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal registered bus transceivers

  SN74ABT8543
Voltage Nodes(V) 5  
Vcc range(V) 4.5 to 5.5  
Input Level TTL  
Logic True  
No. of Outputs 8  
Output Drive(mA) -32/64  
tpd max(ns) 5.5  
Output Level TTL  
Static Current 20  
Rating Catalog  
Technology Family ABT  
SN74ABT8543 特性
  • Members of the Texas Instruments SCOPETM Family of Testability Products
  • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
  • Functionally Equivalent to 'F543 and 'ABT543 in the Normal-Function Mode
  • SCOPETM Instruction Set
    • IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
    • Parallel-Signature Analysis at Inputs With Masking Option
    • Pseudo-Random Pattern Generation From Outputs
    • Sample Inputs/Toggle Outputs
    • Binary Count From Outputs
    • Even-Parity Opcodes
  • Two Boundary-Scan Cells Per I/O for Greater Flexibility
  • State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
  • Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DL) Packages, Ceramic Chip Carriers (FK), and Standard Ceramic DIPs (JT)
SN74ABT8543 芯片订购指南
器件 状态 温度 价格(美元) 封装 | 引脚 封装数量 | 封装载体 丝印标记
SN74ABT8543DW ACTIVE -40 to 85 5.65 | 1ku SOIC (DW) | 28 25 | TUBE  
SN74ABT8543DWE4 ACTIVE -40 to 85 5.65 | 1ku SOIC (DW) | 28 25 | TUBE  
SN74ABT8543DWG4 ACTIVE -40 to 85 5.65 | 1ku SOIC (DW) | 28 25 | TUBE  
SN74ABT8543 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SN74ABT8543DW Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74ABT8543DW SN74ABT8543DW
SN74ABT8543DWE4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74ABT8543DWE4 SN74ABT8543DWE4
SN74ABT8543DWG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74ABT8543DWG4 SN74ABT8543DWG4
SN74ABT8543 应用技术支持与电子电路设计开发资源下载
  1. SN74ABT8543 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器特殊逻辑产品选型与价格 . xls
  3. Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
  4. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  5. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  6. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  7. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  8. Designing With Logic (PDF 186 KB)
  9. Live Insertion (PDF 150 KB)
  10. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  11. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  12. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  13. LOGIC Pocket Data Book (PDF 6001 KB)
  14. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  15. Logic Cross-Reference (PDF 2938 KB)
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