Interfacing any ADC to a microcontroller or microprocessor, whether it is internal or external to the controller, can be challenging, especially when you don't understand all of the issues and trade-offs. Typically, if the controller has an internal ADC, it is an SAR (successive-approximation-register) converter. With an SAR ADC, the primary considerations that you should look at when designing the circuit are the sampling speed of the converter and the converter's external source impedance. If you ignore these fundamental issues, you probably won't get the best out of your converter, whether it is internal or external to your controller. You can easily address these issues in hardware, but this column focuses on the firmware options you can implement.

First, you have to understand the input stage of the SAR ADC. Figure 1 shows a model of the input stage of a typical SAR ADC. Going from left to right, the figure shows the external input impedance as R_S. Usually, if you are driving the SAR converter with an op amp, this impedance is less than a few hundred ohms. But if you are using a higher impedance source, such as a resistive bridge, this impedance can be in the tens of kilohms. The signal passes through R_S into the analog input of the converter. The first internal obstacles that the input signal encounters are the input-pin capacitance, C_PIN, and the ESD diodes. Because these elements have little influence, this column ignores them, along with the leakage current.

Following these elements, the signal reaches the switch resistance, R_SWITCH, and the sampling capacitor, C_SAMPLE. The sampling capacitor represents the bulked element that samples the input signal while the switch is closed. While the converter is sampling the input signal, the combination of the source resistance (R_S), the switch resistance (R_SWITCH), and the sampling capacitor (C_SAMPLE) form a single-pole RC network. The time constant of this network is:

t_RC=(R_S+R_SWITCH)*C_SAMPLE.

Assuming that the charge and voltage on the sample capacitor are zero at the time that it acquires the sample, the rise time of the voltage on that capacitor is equal to: V_CAP=V_IN(1–e^{–t/(RS+RSWITCH)(CSAMPLE)}).

With this formula, you can now determine the percentage of charge that has arrived from the input voltage at the sampling capacitor over time.

If you apply this concept to a specific application in which you use a 12-bit ADC such as the one in Figure 1, you can calculate the number of bits that you have acquired from the input signal. Table 1 illustrates this scenario.

As the table calculates, failing to give the device enough time to sample can compromise the accuracy of an ADC. For instance, use the example of a 12-bit ADC, which samples within 1.5 clock cycles using a clock rate of 2 MHz. The converter allots a sampling time of 750 nsec. This value works well with the numbers in Table 1. Now, add a source resistance of 5 kΩ, and you will find that the converter needs 1350 nsec to accurately convert to 13 bits.

In this instance, I would recommend either slowing the conversion, which you can easily do in firmware, or lowering the source resistance, which could be a more difficult problem to solve.