详细说明：

M74HC138 3 to 8 Line Decoder (Inv.)

The M74HC138 is an high speed CMOS 3 TO 8 LINE DECODER fabricated with silicon gate C2MOS technology.

If the device is enabled, 3 binary select inputs (A, B, and C) determine which one of the outputs will go low. If enable input G1 is held low or either G2A or G2B is held high, the decoding function is inhibited and all the 8 outputs go high. Three enable inputs are provided to ease cascade connection and application of address decoders for memory systems.

All inputs are equipped with protection circuits against static discharge and transient excess voltage.

技术特性

• HIGH SPEED:
  • tPD = 13ns (TYP.) at VCC = 6V
• LOW POWER DISSIPATION:
  • ICC = 4µA(MAX.) at TA=25 °C
• HIGH NOISE IMMUNITY:
  • VNIH = VNIL = 28 % VCC (MIN.)
• SYMMETRICAL OUTPUT IMPEDANCE:
  • |IOH| = IOL = 4mA (MIN)
• BALANCED PROPAGATION DELAYS:
  • tPLH tPHL
• WIDE OPERATING VOLTAGE RANGE:
  • VCC (OPR) = 2V to 6V
• PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 138

M74HC138 订购信息

DATASHEET