详细说明：

AD7725:  内置可编程后处理器的16位Σ-Δ型ADC

AD7725是一款完整的16位、Σ-Δ模数转换器（ADC）,内置片内用户可编程信号调理功能。调制器输出由三个级联的有限脉冲响应（FIR）滤波器及后置的一个用户可编程后处理器处理。用户对滤波器响应、滤波器系数和抽取率拥有完全的控制权。AD7725的额定输入带宽最高可达300 kHz,最大输出字速率为600 kHz。输入采样速率由晶体振荡器或外部时钟设置,额定值为9.6MHz,最大值为14.4MHz。CLKIN频率直接决定器件的最大输入带宽,二者之间的关系式为BW （max） = CLKIN/32。转换数据可通过串行或并行接口获得。为了对后处理器进行编程,可采用配置文件形式将片内默认滤波器或用户自定义滤波器载入器件中。用户自定义滤波器可从具有串行接口的DSP或外部EPROM或者具有并行接口的DSP载入。可以利用名为“滤波器向导”的数字滤波器设计包,产生用户自定义滤波器配置文件。借助此设计包,用户可以设计不同类型的滤波器,并产生相应的配置文件,以便载入器件中。

The AD7725 is a complete 16-bit, sigma-delta analog to digital converter with on chip user-programmable signal conditioning. The output of the modulator is processed by three cascaded finite impulse response (FIR) filters, followed by a user-programmable post processor. The user has complete control over the filter response, the filter coefficients and the decimation ratio.

The AD7725 is specified for input bandwidths up to 300 kHz and an output word rate of 600 kHz maximum. The input sample rate is set either by the crystal oscillator or an external clock, , which has a specified value of 9.6MHz and a maximum value of 14.4MHz. The CLKIN frequency directly determines the maximum input bandwidth of the device with the relationship being BW (max) = CLKIN/32. The conversion data is available via a serial or parallel interface.

To program the Post Processor, either the on-chip, default filter or a user-defined filter in the form of a configuration file can be loaded into the device. The user-defined filter can be loaded from a DSP or an external EPROM with a serial interface or from a DSP with a parallel interface.

The user-defined filter configuration file can be generated using a digital filter design package called 'Filter Wizard'. This package allows the user to design different filter types and generates the appropriate configuration file to be loaded to the device.

AD7725 特点

• 可编程滤波：
  - 最高108 阶FIR和/或IIR的任何特性
• 多项式信号调理,最高八阶
• 灵活的编程模式：
  - 从DSP或外部EPROM导入
  - 并行/串行接口
• 评估用内部默认滤波器
• 可编程抽取和输出字速率
• 主时钟频率：最大14.4 MHz
• 输入范围：0 V至+4 V（单端）或±2 V（差分）
• AVDD,DVDD电源：5 V ± 5%
• 2.5 V片内基准电压
• 44引脚MQFP封装
• Programmable Filtering- Any Characteristic up to 108 Tap FIR and/or IIR
• Polynomial Signal Conditioning up to 8th Order
• Flexible Programming Modes
  - Boot from DSP or External EPROM
  - Parallel/Serial Interface
• Internal Default Filter for Evaluation
• Programmable Decimation and Output Word Rate
• 14.4 MHz Max Master Clock Frequency
• 0 V to +4 V (Single-Ended) or ±2 V (Differential) Input Range
• Power Supplies: AVDD, DVDD: 5 V ± 5%
• On-Chip 2.5 V Voltage Reference
• 44-Lead MQFP Package

AD7725 技术指标

• Resolution (Bits): 16bit
• # Chan: 1
• Sample Rate: 14.4MSPS
• Interface: Par,Ser
• Analog Input Type: Diff-Bip,SE-Uni
• Ain Range: 4 V p-p,Uni 4.0V
• ADC Architecture: Sigma-Delta
• Pkg Type: QFP

AD7725 功能框图

AD7725 芯片订购指南

AD7725 应用技术支持与电子电路设计开发资源下载

1. AD7725 数据手册DataSheet下载 .PDF
2. Analog Devices, Inc.ADI 美国模拟器件公司产品订购手册 .PDF
3. ADC模数转换器选型指南 . PDF