Multi-DSPLL Wireless Jitter Attenuating Clocks
The Si5381/82 is a wireless multi-PLL, jitter-attenuating clock that leverages Silicon Labs’ latest fourth-generation DSPLL technology to address the form factor, power, and performance requirements demanded by radio area network equipment, such as small cells, baseband units, and distributed antenna systems (DAS). The Si538x is the indus-try’s first multi-PLL wireless clock generator family capable of replacing discrete, high-performance, VCXO-based clocks with a fully integrated CMOS IC solution. The Si5381/82 features a multi-PLL architecture that supports independent timing paths for JESD wireless clocks with less than 85 fs typical phase jitter as well as Ethernet and other low-jitter, general-purpose clocks. DSPLL technology also supports free-run and holdover operation as well as automatic and hitless input clock switching. This unparalleled integration reduces power and size without compromising the stringent performance and reliability demanded in wireless applications.

Applications
• Pico cells, small cells
• Mobile backhaul
• Multiservice Distributed Access Systems (MDAS)